DocumentCode :
263174
Title :
Parallel implementation of a sample rate conversion and pulse-shaping filter for high speed backhauling networks
Author :
Alonso, Aritz ; Sevillano, Juan Francisco ; Velez, Igone
Author_Institution :
Dept. of Electron. & Commun., Univ. of Navarra, San Sebastián, Spain
fYear :
2014
fDate :
26-28 Nov. 2014
Firstpage :
1
Lastpage :
6
Abstract :
This paper considers the design of a parallel sample rate interpolation filter for the backhaul of the future mobile networks. These future networks must provide Gigabit data rates, which relay on the use of high spectral efficiency, high bandwidth baseband signals. Parallel signal processing becomes a necessity since state of the art technology is incapable of serially generating and converting these high bandwidth signals. Moreover, signal generation and digital-to-analog conversion are performed under incommensurate clock domains. Therefore, interpolation becomes a necessity when connecting signal generation to signal conversion. The paper analyses the interpolation equation and discusses several techniques to achieve a parallel implementation. The designed interpolation filter has been tested to adapt an incoming signal data stream at a rate of 1.7 giga-symbols per second into a stream of interpolants at a rate of 2.8 giga-interpolants per second under two incommensurate clock domains.
Keywords :
digital-analogue conversion; filtering theory; interpolation; mobile communication; pulse shaping; signal sampling; digital-to-analog conversion; gigabit data rate; high bandwidth baseband signal; high speed backhauling network; incommensurate clock domain; mobile network; parallel sample rate interpolation filter; parallel signal processing; pulse-shaping filter; sample rate conversion; signal data stream; signal generation; spectral efficiency; Adders; Clocks; Communication systems; Indexes; Interpolation; Pulse shaping methods; Vectors; Filtering; High Speed; Interpolation; Parallel implementation; Sample Rate Conversion;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design of Circuits and Integrated Circuits (DCIS), 2014 Conference on
Conference_Location :
Madrid
Type :
conf
DOI :
10.1109/DCIS.2014.7035555
Filename :
7035555
Link To Document :
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