Title :
Memory BIST for on-chip monitoring of resistive-open defects due to electromigration and stress-induced voiding in an SRAM array
Author :
Woongrae Kim ; Soonyoung Cha ; Milor, Linda
Author_Institution :
Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
We present a Built-in Self Test (BIST) methodology for on-chip failure analysis of via/contact voiding due to electromigration (EM) and stress-induced voiding (SIV) in SRAM cells. Our BIST system aims to detect wearout in faulty cells and identify the location of the failure in the cell. This enables more efficient physical failure analysis.
Keywords :
SRAM chips; built-in self test; electromigration; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; vias; voids (solid); SRAM array; electromigration; memory BIST; on-chip failure analysis; on-chip monitoring; resistive open defect; stress induced voiding; via-contact voiding; Algorithm design and analysis; Built-in self-test; Circuit faults; Fault diagnosis; Maintenance engineering; Resistance; SRAM cells;
Conference_Titel :
Design of Circuits and Integrated Circuits (DCIS), 2014 Conference on
Conference_Location :
Madrid
DOI :
10.1109/DCIS.2014.7035560
