Recoded and nonrecoded trinary signed-digit multipliers designs using redundant bit representations

Author

Cherri, Abdallah K. ; Alam, Mohammed S.

Author_Institution

Dept. of Electr. & Comput. Eng., Kuwait Univ., Safat, Kuwait

fYear

1998

fDate

13-17 Jul 1998

Firstpage

505

Lastpage

512

Abstract

Recently, highly-efficient two-step recoded and one-step nonrecoded trinary signed-digit (TSD) carry-free adder/subtracter has been presented based on redundant bit representation (RBR) for the operands digits where it has been shown that only 24 (30) minterms are needed to implement the two-step recoded TSD (the one-step nonrecoded) addition for any operand length. In this paper, we present four different multiplication designs based on our proposed recoded and nonrecoded TSD adders. Our multiplication designs require a small number of reduced minterms to generate the multiplication partial products

Keywords

digital arithmetic; logic design; multiplying circuits; optical computing; redundancy; carry-free adder/subtracter; multiplication designs; multiplication partial products; one-step process; redundant bit representations; trinary signed-digit multipliers; two-step process; Adders; Digital arithmetic; Educational institutions; Equations; High speed optical techniques; Image processing; Iterative algorithms; Parallel processing; Petroleum; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace and Electronics Conference, 1998. NAECON 1998. Proceedings of the IEEE 1998 National

Conference_Location

Dayton, OH

ISSN

0547-3578

Print_ISBN

0-7803-4449-9

Type

conf

DOI

10.1109/NAECON.1998.710183

Filename

710183