A design-space exploration tool for low-power DCT and IDCT hardware accelerators

Author

Walters, E. George, III

Author_Institution

Penn State Erie, Behrend Coll., Erie, PA, USA

fYear

2012

fDate

4-6 June 2012

Firstpage

1

Lastpage

5

Abstract

The discrete cosine transform (DCT) and its inverse (IDCT) are often used for image compression and decompression. Truncated-matrix multipliers offer reduced area, power and delay at the expense of increased computational error. This paper describes a software tool for design-space exploration of low-power DCT and IDCT hardware accelerators that use truncated-matrix multipliers. The tool has an interactive graphical user interface and is written entirely in Java. It can open image files, simulate compression and/or decompression, and display the processed image and error statistics.

Keywords

Java; data compression; discrete cosine transforms; error statistics; graphical user interfaces; image coding; interactive systems; inverse transforms; matrix multiplication; multiplying circuits; software tools; Java; design space exploration tool; discrete cosine transform; error statistics; image compression; image decompression; image files; image processing; interactive graphical user interface; inverse discrete cosine transform; low-power DCT hardware accelerator; low-power IDCT hardware accelerator; software tool; truncated-matrix multipliers; Delay; Discrete cosine transforms; Error analysis; Image coding; PSNR; Quantization; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics (ISCE), 2012 IEEE 16th International Symposium on

Conference_Location

Harrisburg, PA

ISSN

0747-668X

Print_ISBN

978-1-4673-1354-4

Type

conf

DOI

10.1109/ISCE.2012.6241736

Filename

6241736