Title :
Testing of analog neural array-processor chips
Author :
Hsu, Wen-jay ; Sheu, Bing J. ; Gowda, Sudhir M.
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
A systematic approach to test analog array-processor neural chips is presented. Unique testing problems for analog neural chips are described and effective solutions are discussed. Based on the hierarchical methodology, testing of analog array-processor neural chips can be systematically addressed. The test results for programmable analog neural chips fabricated by a 2-μm CMOS process are presented. These chips contain 25 neurons and 1600 synapses
Keywords :
CMOS integrated circuits; analogue computer circuits; integrated circuit testing; neural nets; CMOS process; analog array-processor neural chips; analog neural array-processor chips; chip testing; neurons; programmable analog neural chips; synapses; Analog circuits; Circuit faults; Circuit testing; Dynamic range; Neural network hardware; Neurons; Signal processing; System testing; Very large scale integration; Voltage control;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
DOI :
10.1109/ICCD.1991.139859
