Hardware architecture for Kohonen network

Author

Onodera, Hidetoshi ; Takeshita, Kiyoshi ; Tamaru, Keilcichj

Author_Institution

Dept. of Electron., Kyoto Univ., Japan

fYear

1990

fDate

1-3 May 1990

Firstpage

1073

Abstract

A fully digital architecture for Kohonen networks suitable for VLSI implementation is proposed. The architecture has a structure similar to a content addressable memory (CAM). One work of CAM is regarded as a processing element, and a group of elements forms a neuron. All processing elements execute the same operation in bit-serial but in processor-parallel. Thus, the number of instructions for realizing the network algorithm is independent of the number of neurons in the network. With reference to a previously reported CAM, it is estimated that a network with 96 neurons for speech recognition could be integrated on three chips and that it would operate 50 times faster than sequential hardware. Owing to its highly regular structure of memories, the proposed hardware architecture is compatible with current VLSI technology

Keywords

VLSI; content-addressable storage; digital integrated circuits; hybrid computers; neural nets; parallel architectures; Kohonen networks; VLSI implementation; content addressable memory; digital architecture; hardware architecture; highly regular structure; speech recognition; Associative memory; CADCAM; Computer aided manufacturing; Hardware; Lattices; Neurons; Signal processing; Space technology; Speech recognition; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112295

Filename

112295