Title :
A novel three-phase software phase-locked loop based on frequency-locked loop and initial phase angle detection phase-locked loop
Author :
Wang, Liang ; Jiang, Qirong ; Hong, Lucheng
Author_Institution :
Dept. of Electr. Eng., Tsinghua Univ., Beijing, China
Abstract :
This paper proposes a new three-phase software phase-locked loop (SPLL) which operates fast and accurately in unbalanced, polluted and frequency deviated circumstances. This new proposed SPLL consists of frequency-locked loop (FLL) and initial phase angle detection PLL. The FLL employs differential algorithm to detect frequency error which could immune to phase jumps and voltage sharp changes. A frequency adaptive digital filter (FADF) is included in FLL to reject harmonics. The FADF uses two strategies to sweep away disturbing signals in a synchronous reference domain. Firstly, specific order harmonics are eliminated by multistage application of delayed signal cancellation (DSC) using estimated delayed signals. Excellent steady-state performance of multistage DSC to reject harmonics is achieved with the help of FLL and interpolation strategy. Secondly, a conventional low-pass (LP) filter damps the rest higher frequency harmonics and noises. Initial phase angle detection PLL could have a high cutoff frequency due to good performance of FADF. Simulations prove the new SPLL responds fast and has precise steady-state output.
Keywords :
adaptive filters; digital filters; frequency locked loops; interpolation; low-pass filters; phase detectors; phase locked loops; power grids; power harmonic filters; FADF; FLL; LP filter; SPLL; cutoff frequency; delayed signal cancellation; delayed signal estimation; differential algorithm; frequency adaptive digital filter; frequency error detection; frequency-locked loop; harmonic rejection; harmonics frequency; initial phase angle detection phase-locl<;ed loop; interpolation strategy; low-pass filter; multistage DSC; phase jump; power grid; signal disturbance; specific order harmonic elimination; synchronous reference domain; three-phase software phase-locked loop; voltage sharp; Delayed Signal Cancellation; Digital Filter; Frequency-Locked Loop; Grid Synchronization; Software Phase-Locked Loop;
Conference_Titel :
IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics Society
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-2419-9
Electronic_ISBN :
1553-572X
DOI :
10.1109/IECON.2012.6388816