A simple visualizing technique of impurity diffusion layer using porous silicon phenomena

We propose an approach to visualize the impurity diffusion layer at a specific site in sub-100 nm CMOS devices using the porous silicon phenomena. This technique is based on electron microscope observations of samples which have been wet treated using self-aligned anodic oxidation in aqueous hydrofluoric acid. This can be applied to both NMOS transistors and PMOS transistors using the same procedure simultaneously in sub-100 nm CMOS transistors. A clear dopant distribution of source/drain and lightly doped drain (LDD) diffusion layers was obtained with not only transmission electron microscope, but also scanning electron microscope. This technique shows excellent reproducibility and stability, which have been critical issues with wet processing methods. In addition, a failure involving the highly-resistive electrical characteristics in the 90 nm-node transistor was analyzed. As a result, it was found that the failure was caused by a local block of LDD ion implantation. Our analysis revealed that visualizing the impurity diffusion layer using this technique can be applied to the fine CMOS devices at a specific site.