DocumentCode :
2633308
Title :
Low-к - package integration challenges and options for reliability qualification
Author :
Lucero, A.E. ; Guanghai Xu ; Huitink, David
Author_Institution :
Assembly Technol. Dev., Quality & Reliability, Intel Corp., Chandler, AZ, USA
fYear :
2012
fDate :
15-19 April 2012
Abstract :
Traditional packaging materials and reliability standards are evolving as low-κ die - package integration challenges increase. The dielectric constants of low-κ die interlayer dielectric (ILD) materials are expected to continue to reduce to manage Resistance/Capacitance, RC, delay as interconnect and cell geometries are reduced. Mechanical strength is also reduced with the improvement in dielectric constant. The scaling of mechanical strength properties must be considered when designing packaging and selecting materials for packaging and assembly. Die-package integration challenges are most often observed when placing large die on flipchip packages where the differences of the coefficient of thermal expansion, CTE, between the package and die become more pronounced. In particular the underfill material and Si backend must be designed to mitigate the CTE difference by having adequate strength to carry or buffer the interfacial loads without exerting enough force to pull off the die stack films, bump interconnect or package films while at use temperatures. Properties like viscosity must also be managed for successful assembly processing. Underfill materials properties are typically coupled with the glass transition temperature, Tg, which means that the CTE and modulus properties that are required for successful assembly, use performance and reliability of the die-package system are fixed to narrow ranges. Traditional reliability standard testing and requirements do no comprehend the new reality where the Tg often falls below the traditional reliability stress test temperature. New stress test standards released by JEDEC show that lower reliability test levels with longer durations can be used to insure end user reliability in the customer use conditions. New standards have not yet been adopted by many parts of the industry, resulting in false failures and inaccurate risk assessments when the accelerated reliability test temperature ranges cause consti- uent materials to be artificially tested at conditions where materials properties are non-linear. Fortunately, there are many reliability characterization, analysis and reliability estimation methods that can be used to protect the end user. This paper summarizes the die-package integration challenges and trends that the industry is starting to experience along with options to select, evaluate and qualify reliable products.
Keywords :
dielectric materials; electronics packaging; flip-chip devices; mechanical strength; permittivity; reliability; assembly processing; bump interconnect; die stack films; dielectric constants; flipchip packages; glass transition temperature; low-κ die interlayer dielectric materials; low-κ die-package integration; low-κ-package integration; mechanical strength; modulus properties; package films; packaging materials; reliability estimation; reliability qualification; reliability standard testing; reliability standards; reliability stress test temperature; underfill materials properties; viscosity; Dielectric constant; Materials reliability; Silicon; Stress; Temperature; Die-package; JEDEC; Low-к; dielectric; underfill;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium (IRPS), 2012 IEEE International
Conference_Location :
Anaheim, CA
ISSN :
1541-7026
Print_ISBN :
978-1-4577-1678-2
Electronic_ISBN :
1541-7026
Type :
conf
DOI :
10.1109/IRPS.2012.6241789
Filename :
6241789
Link To Document :
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