Title :
On-chip multiple superscalar processors with secondary cache memories
Author :
Hanawa, M. ; Nishimukai, T. ; Nishii, O. ; Suzuki, M. ; Yano, K. ; Hiraki, M. ; Shukuri, S. ; Nishida, T.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
The development of an experimental high-performance microprocessor chip based on a 0.3-μm BiCMOS technology is discussed. It is designed to operate at a 250-MHz clock rate. It includes two processors, each of which executes two instructions in parallel. The chip performs 1000 MIPS when instructions and data are fetched from primary caches. It also includes a four-wave interleaved secondary cache assessed in parallel according to a split-bus protocol, to reduce shared memory conflicts. The VLSI architecture and design results of this chip are described
Keywords :
BIMOS integrated circuits; VLSI; buffer storage; microprocessor chips; multiprocessing systems; 0.3 micron; 1000 MIPS; 250 MHz; BiCMOS technology; VLSI architecture; clock rate; four-wave interleaved secondary cache; microprocessor chip; on-chip multiple superscalar processors; primary caches; secondary cache memories; shared memory conflicts; split-bus protocol; Access protocols; BiCMOS integrated circuits; Cache memory; Central Processing Unit; Clocks; Laboratories; Large-scale systems; Microprocessor chips; System-on-a-chip; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
DOI :
10.1109/ICCD.1991.139862
