Title :
All-out fight against yield losses by design-manufacturing collaboration in nano-lithography era
Author :
Inoue, Soichi ; Kobayashi, Sachiko
Author_Institution :
Adv. Lithography Process Technol. Dept., Toshiba Corp., Kawasaki, Japan
Abstract :
The concept of design-manufacturing collaboration for nano-lithography era has been clarified. The novel design-manufacturing system that the manufacturing tolerance reflecting design intention properly can be allocated to the layout has been proposed. According to the system, one can assign the “weak portion” explicitly on the layout, and can control the process for reducing the burden of manufacturing and further getting higher yield. More specifically, the extraction of electrically critical portion and conversion to the manufacturing tolerance has been demonstrated. The tolerance has applied to reduce computational burden of mask data preparation. Besides, the yield model-based layout scoring system has been also suggested to be significant remarkably. One can check the layout and modify not to loose the yield. Creation of yield function, layout scoring, and layout modification based upon the yield model have been demonstrated.
Keywords :
design for manufacture; integrated circuit layout; integrated circuit yield; masks; nanolithography; all-out fight against yield losses; computational burden; design intention; design-manufacturing collaboration; design-manufacturing system; electrically critical portion; layout modification; manufacturing tolerance; mask data preparation; nano-lithography era; yield function; yield model-based layout scoring system; Collaboration; Crosstalk; Layout; Lithography; Logic gates; Optimization;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-7515-5
DOI :
10.1109/ASPDAC.2011.5722220