A self-learning neural network composed of 1152 digital neurons in wafer-scale LSIs

The design, fabrication, and evaluation of a compact self-learning neural network made up of more than 1000 neurons are described. A time-sharing bus architecture decreases the number of circuits required and makes possible flexible and expandable networks. Neural functions and the back propagation (BP) algorithm were mapped to binary digital circuits. A dual-network architecture allows high-speed learning. This hardware can be connected to a host workstation and used for a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware. The peak learning speed was about 10 times faster than BP simulation by an S-820 Hitachi supercomputer