Process technology for 3D-CMOS devices

Summary form only given. A 2-μm three-dimensional CMOS process which allows the fabrication of MOS devices in two layers is discussed. NMOS devices in the silicon substrate and CMOS devices were realized, as inverters and ring oscillators, in a 0.5-μm-thick recrystallized polysilicon layer. The as-deposited polysilicon upper device layer is recrystallized by means of an argon laser system. The influence of different recrystallization parameters on substrate damage was studied. On the basis of these investigations a high-quality SOI layer was obtained without generating any crystal damage in the underlying silicon. This was confirmed by the electrical characteristics of the fabricated MOS devices, which do not show any degradation as compared with customary bulk devices. An undesired effect is the occurrence of mass transport upon recrystallization of the silicon film. While with the standard film thickness of 0.5 μm this is no problem, thin-film SOI MOS transistors (thickness about 0.1 μm) exhibit improved properties. Therefore measures to minimize mass transport are being studied to allow the thinning of recrystallized silicon layers and to fabricate thin-film SOI devices