A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling

In this paper, we introduce a 3 valued MVCM 4-phase link, where cores at each end of the link use 4-phase dual-rail protocol. The dual-rail N-bit data are encoded onto N + 1 wires on the link, thus reducing the number of interconnects between cores and improving power and crosstalk features. We show that it is impractical to encode a 2-phase dual-rail asynchronous data bit onto one wire using MVCM signaling, which was used in previous works, as it generates an unavoidable hazard at the receiver end. The main advantage of our design is that it does not generate any hazards. To evaluate our claim, we use a simple transmitter and receiver implemented in 130 nm technology. Results show a hazard-free communication over different link lengths in contrast to previous works.