• DocumentCode
    2633733
  • Title

    Fat-tree for local area multiprocessors

  • Author

    Li, Qiang ; Gustavson, David

  • Author_Institution
    Dept. Comput. Eng., Santa Clara Univ., CA, USA
  • fYear
    1995
  • fDate
    25-28 Apr 1995
  • Firstpage
    32
  • Lastpage
    36
  • Abstract
    The local area multiprocessor (LAMP) is a newly-feasible approach for achieving high-performance low-cost parallel computing. LAMP allows a large number of machines distributed over a LAN-size area to operate as a distributed-shared-memory multiprocessor. Latency is kept low by using the scalable coherent interface and by caching remote data. SCI keeps the caches consistent and provides a high performance multiprocessor “bus” using only point-to-point physical connections (links), which can operate at far higher speeds than any bus. Large numbers of links may be used concurrently for extremely high system throughput, interconnected by a packet switch using any of a wide range of topologies and technologies. This paper examines the use of a fat-tree topology for this (possibly distributed) switch. Simulation results are presented to show the latency, throughput, buffer requirements, and the effect of cable length. Link clock speeds assumed are 250 MHz (GaAs or biCMOS chips) and 32 MHz (CMOS)
  • Keywords
    cache storage; distributed memory systems; local area networks; multiprocessor interconnection networks; packet switching; parallel architectures; performance evaluation; shared memory systems; system buses; CMOS; LAMP; LAN-size area; SCI; biCMOS chips; buffer requirements; cable length; distributed-shared-memory multiprocessor; fat-tree topology; high performance multiprocessor; high system throughput; high-performance low-cost parallel computing; latency; link clock speeds; local area multiprocessors; packet switch; parallel architecture; point-to-point physical connections; remote data cache; scalable coherent interface; simulation results; CMOS technology; Clocks; Delay; Gallium arsenide; Lamps; Packet switching; Parallel processing; Switches; Throughput; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing Symposium, 1995. Proceedings., 9th International
  • Conference_Location
    Santa Barbara, CA
  • Print_ISBN
    0-8186-7074-6
  • Type

    conf

  • DOI
    10.1109/IPPS.1995.395910
  • Filename
    395910