DocumentCode
2633826
Title
A heuristic algorithm to design AND-OR-EXOR three-level networks
Author
Debnath, Debatosh ; Sasao, Tsutomu
Author_Institution
Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
fYear
1998
fDate
10-13 Feb 1998
Firstpage
69
Lastpage
74
Abstract
An AND-OR-EXOR network, where the output EXOR gate has only two inputs, is one of the simplest three-level architecture. This network realizes an EXOR of two sum-of-products expressions (EX-SOP). In this paper, we show an algorithm to simplify EX-SOPs for multiple-output functions. Our objective is to minimize the number of distinct products in the sum-of-products expressions of EX-SOPs. The algorithm uses a divide-and-conquer strategy. It recursively applies the Shannon decomposition on a function with more than five variables. The algorithm obtains EX-SOPs for the five-variable functions by using an exact minimization program, then combines those EX-SOPs to generate EX-SOPs for the functions with more variables. We present experimental results for a set of benchmark functions, and show that EX-SOPs require many fewer products and literals than sum-of-products expressions. This is evidence that AND-OR-EXOR is a powerful architecture to realize many practical logic functions
Keywords
minimisation of switching nets; ternary logic; AND-OR-EXOR; AND-OR-EXOR network; divide-and-conquer; heuristic algorithm; logic functions; minimisation; three-level architecture; Adders; Algorithm design and analysis; Arithmetic; Circuits; Computer science; Heuristic algorithms; Logic devices; Logic functions; Programmable logic arrays; Programmable logic devices;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
0-7803-4425-1
Type
conf
DOI
10.1109/ASPDAC.1998.669404
Filename
669404
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