An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs

Satisfying clock skew constraint is one of the most important tasks in the clock tree synthesis. Moreover, the task becomes much harder to solve as the clock tree is designed under multiple power mode environment, in which the voltage applied to some design module varies as the power mode changes. Recently, it is shown that adjustable delay buffer (ADB) whose delay can be tuned dynamically can be used to solve the clock skew problem effectively under multiple power modes. However, due to the area/control overhead by ADBs it is very important to minimize the number of ADBs. This work provides a complete solution to the problem of clock skew minimization using ADBs under multiple power modes. We propose a linear-time optimal algorithm that simultaneously solves the problems of computing (1) the minimum number of ADBs to be used, (2) the location at which each ADB is to be placed, and (3) the delay value of each ADB to be assigned to each power mode. Experimental results show that in comparison with the previous work [8] which iteratively performs the ADB allocation, placement, and delay assignment, our integrated algorithm produces consistently better designs for all tested benchmarks under four power modes, reducing the number of ADBs by 9.27% further on average at skew bound of 30ps~50ps even with shorter clock latencies.