On applying erroneous clock gating conditions to further cut down power

All of today´s known clock gating techniques only disable clocks on valid (”correct”) clock gating conditions, like idle states or observability don´t cares (ODC), whose applying will not change the circuit functionality. In this paper, we explore a technique that allows shutting down certain clocks during invalid cycles, which if applied alone will certainly cause erroneous results. However, the erroneous results will be corrected either during the current or later stages by injecting other clock gating conditions to cancel out each other´s error effects before they reach the primary outputs. Under this model, conditions across multiple flip-flop stages can also be analyzed to locate easily correctable erroneous clock gating conditions. Experimental results show that by using this error cancellation technique, a total power (including dynamic and leakage power) cut of up to 23% and in average of around 6% could be stably achieved, no matter with or without applying Power Compiler (which brought a power cut of 4% in average) together. The results indicate that the power saving conditions found by this new technique were nearly orthogonal (independent) to what can be done by the popular commercial power optimization tool. The idea of these new multi-stage logic error cancellation operations can potentially be applied to other sequential logic synthesis problems as well.