DocumentCode
2634118
Title
A predictive bottom-up hierarchical approach to digital system reliability
Author
Huard, V. ; Pion, E. ; Cacho, F. ; Croain, D. ; Robert, V. ; Delater, R. ; Mergault, P. ; Engels, S. ; Flatresse, P. ; Amador, N. Ruiz ; Anghel, L.
Author_Institution
STMicroelectron., Crolles, France
fYear
2012
fDate
15-19 April 2012
Abstract
This work has introduced a new electrical aging assessment framework for digital systems, based upon strong physics-based foundations and an adequate bottom-up approach which enables propagating accurate reliability knowledge at system level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy.
Keywords
ageing; integrated circuit reliability; integrated circuit testing; life testing; system-on-chip; digital system reliability; electrical aging assessment framework; life test; predictive bottom-up hierarchical approach; system-on-chip; Degradation; Human computer interaction; Integrated circuit reliability; Logic gates; Mathematical model; Timing; HCI; NBTI; aging assessment framework; composite model; derate margin; gate models; operating lifetests; reaction-diffusion model; reliability; signal probability; system-on-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium (IRPS), 2012 IEEE International
Conference_Location
Anaheim, CA
ISSN
1541-7026
Print_ISBN
978-1-4577-1678-2
Electronic_ISBN
1541-7026
Type
conf
DOI
10.1109/IRPS.2012.6241830
Filename
6241830
Link To Document