DocumentCode :
2634148
Title :
Session Abstract
fYear :
2007
fDate :
39203
Firstpage :
43
Lastpage :
43
Abstract :
Today¿s designs are constrained by performance targets, power and energy requirements, reliability concerns, and by yield targets. Simultaneously optimizing these many constraints becomes more difficult in the presence of variations -- both static process variations and dynamic fluctuations in voltage, temperature, and transistor degradation. Typically these variations are guardbanded so that the design runs at a lower performance or at a higher power than would be required. However, as power envelopes continue to shrink while the magnitude of many variations increases, the guardbanding approach becomes too expensive. A combination of variation-tolerant design techniques, design for manufacturing, and adaptive response to dynamic variations is necessary to arrive at the most efficient design.
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2007. 25th IEEE
Conference_Location :
Berkeley, CA, USA
ISSN :
1093-0167
Print_ISBN :
0-7695-2812-0
Type :
conf
DOI :
10.1109/VTS.2007.66
Filename :
4209889
Link To Document :
بازگشت