Optimizing Test Length for Soft Faults in DRAM Devices

Author

AL-Ars, Zaid ; Hamdioui, Said ; Gaydadjiev, Georgi

Author_Institution

Fac. of EE, Math. & CS, Delft Univ. of Technol.

fYear

2007

fDate

6-10 May 2007

Firstpage

59

Lastpage

66

Abstract

Soft faults in DRAMs are faults that do not get sensitized directly after an operation is performed, but require a time to pass before the fault can be detected. Tests developed to detect these faults are rather complex and take an exceptionally long time to apply on the memory. This paper discusses a number of methods to optimize the test length for soft faults, based on the electrical design of the memory and the topology of the layout. These methods make it possible to reduce the delay time needed in the test such that it does not scale with the number of cells in the memory

Keywords

DRAM chips; fault diagnosis; optimisation; DRAM devices; DRAM testing; fault detection; soft faults; test length optimization; Circuit faults; Circuit testing; Delay effects; Design optimization; Electrical fault detection; Fault detection; Logic; Optimization methods; Random access memory; Resource description framework; DRAM testing; circuit design; delay time.; memory layout; soft faults; test length optimization;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2007. 25th IEEE

Conference_Location

Berkeley, CA

ISSN

1093-0167

Print_ISBN

0-7695-2812-0

Type

conf

DOI

10.1109/VTS.2007.46

Filename

4209892