DocumentCode
2634342
Title
On a New Outlier Rejection Technique
Author
Thibeault, C.
Author_Institution
Dept. of Electr. Eng., Ecole de technologie superieure, Montreal, Que.
fYear
2007
fDate
6-10 May 2007
Firstpage
97
Lastpage
103
Abstract
This paper presents a novel approach to reject outliers based on parametric measurements, namely quiescent current and IC speed estimates. Unlike the existing multi-parameter or IDDQ-based techniques which use additional measurements to estimate the expected healthy IDDQ response, the authors focus on the variance to reject outliers. The authors take advantage of the correlation between the two types of measurements and of the fact that speed estimate measurements are more reliable than leakage ones in order to evaluate the acceptable current variation level. For that, the authors derive approximate variance equations from basic current and delay equations. Using these variance equations, the authors are able to identify current variations that cannot be justified by normal process variations, based on simple outlier rejection criteria. This approach is developed to be used as a pre-processing tool to other post-processing techniques. Results are promising.
Keywords
integrated circuit testing; current testing; current variation level; integrated circuit testing; outlier rejection; variance equations; Circuit testing; Current measurement; Delay estimation; Equations; Filters; Leakage current; Performance evaluation; Robustness; Velocity measurement; Yield estimation; Multi-parameter testing; current testing.;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2007. 25th IEEE
Conference_Location
Berkeley, CA
ISSN
1093-0167
Print_ISBN
0-7695-2812-0
Type
conf
DOI
10.1109/VTS.2007.44
Filename
4209897
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