Diagnosis of Full Open Defects in Interconnecting Lines

Author

Rodríguez-Montanés, R. ; Arumi, D. ; Figueras, J. ; Einchenberger, S. ; Hora, C. ; Kruseman, B. ; Lousberg, M. ; Majhi, A.K.

Author_Institution

Dept. d´´Enginyeria Electronica, Univ. Politecnica de Catalunya, Barcelona

fYear

2007

fDate

6-10 May 2007

Firstpage

158

Lastpage

166

Abstract

A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.

Keywords

CMOS integrated circuits; fault diagnosis; integrated circuit testing; CMOS circuits; circuit under test; defect diagnosis; full open defect; integrated circuit testing; interconnecting lines; quiescent current; CMOS technology; Capacitance; Circuit testing; Circuit topology; Integrated circuit interconnections; Logic circuits; Logic gates; Logic testing; Proposals; Threshold voltage; CMOS.; Defect Diagnosis; Full Open Defect; Interconnecting Line;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2007. 25th IEEE

Conference_Location

Berkeley, CA

ISSN

1093-0167

Print_ISBN

0-7695-2812-0

Type

conf

DOI

10.1109/VTS.2007.28

Filename

4209906