Session Abstract

This session focuses on issues and challenges of high-speed test, including Gbps serial or parallel interfaces, high-speed clocks and PLLs. Contributors are invited to present their novel practices in solving high-speed test and device characterization issues, including high-speed data capture, bit-error-rate test, and signal integrity, e.g., timing/jitter and voltage tests. Example concepts are DFT and BIST schemes, ATE-based solutions, high-speed test quality and economy, application-dependent test resource partitioning strategies, characterization and final test correlation, jitter and phase-noise test, structural test approaches, etc.