A New Cycle-Stealing Technique for Pipelined Instruction Decompression System for Microprocessors

A cycle stealing technique has been presented for avoiding the delays for instruction decompression when branching and cache missing occur. However, its cost is relatively high and it can´t deal with exceptions. A new cycle-stealing technique is presented to reduce the cost and deal with exception handlings. The simulation results for several benchmarks show that the average benefit, the saving of area, is about 25%.