DocumentCode
2634666
Title
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video
Author
Chien, Cheng-An ; Yang, Yao-Chang ; Chang, Hsiu-Cheng ; Chen, Jia-Wei ; Chang, Cheng-Yen ; Guo, Jiun-In ; Wang, Jinn-Shyan ; Cheng, Ching-Hwa
Author_Institution
Dept. CSIE / EE, Nat. Chung-Cheng Univ., Chiayi, Taiwan
fYear
2011
fDate
25-28 Jan. 2011
Firstpage
73
Lastpage
74
Abstract
This paper proposes a dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width. A design automation environment for simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 um CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2~328mW in decoding CIF~HD1080 videos at 3.75~30fps when operating at 1~150MHz, respectively.
Keywords
SRAM chips; video codecs; video coding; CMOS technology; H.264-MPEG-2; SRAM; adjustable memory bus width; dual mode video decoder chip; size 0.13 mum; temporal-spatial scalable video; Decoding; High definition video; Random access memory; Scalability; Static VAr compensators; Streaming media; Transform coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific
Conference_Location
Yokohama
ISSN
2153-6961
Print_ISBN
978-1-4244-7515-5
Type
conf
DOI
10.1109/ASPDAC.2011.5722284
Filename
5722284
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