Access order to avoid inter-vector-conflicts in complex memory systems

The performance of a vector processor accessing vectors is strongly dependent on the conflicts produced in the memory subsystem. The concurrent memory access of several vector streams causes inter-conflicts between the references of different vectors. In a complex memory system (several memory modules are mapped in every bus) the number of conflicts increases because the bus must be shared by the vector streams. This paper proposes a method that allows a concurrent access to several vector streams reducing the average memory access time in vector processors with complex memory systems