Session Abstract

Is reliability going to be the ultimate barrier to CMOS scaling? Reliability failure modes such as soft errors, erratic bits, transistor aging and infant mortality challenge us now more than ever. Will there be an end to burn-in as we know it? Will system design be able to take some of the load off of the individual IC? This session will deal with the reliability challenges in scaled CMOS, their implications to test, and the emerging role of system design in building reliable systems out of ICs that tend sometimes to fail.