Title :
A Dividing Ratio Changeable Digital PLL with Low Output Phase Noise
Author :
Fujimoto, Kuniaki ; Yahara, Mitsutoshi ; Sasaki, Hirofumi ; Shi, Yan
Author_Institution :
Sch. of Ind. Eng., Tokai Univ., Tokai
Abstract :
In this paper, the dividing ratio changeable digital phase locked loop (DCPLL) which is difficult to receive the effect of the input phase noise is proposed. This circuit can realize the characteristic of a wide lock-in range and a fast pull-in.
Keywords :
circuit noise; digital phase locked loops; dividing circuits; phase noise; dividing ratio changeable digital PLL; input phase noise; lock-in range; output phase noise; phase locked loop; Clocks; Counting circuits; Detectors; Educational institutions; Frequency conversion; Industrial engineering; Jitter; Phase detection; Phase locked loops; Phase noise;
Conference_Titel :
Innovative Computing Information and Control, 2008. ICICIC '08. 3rd International Conference on
Conference_Location :
Dalian, Liaoning
Print_ISBN :
978-0-7695-3161-8
Electronic_ISBN :
978-0-7695-3161-8
DOI :
10.1109/ICICIC.2008.25
