A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS

We have designed and measured the performance against power supply bounce and aging of a Self Synchronous FPGA (SSFPGA) in 65nm CMOS which achieves 2.97GHz throughput at 1.2V. The proposed SSFPGA employs a 38×38 array of 4-input, 3-stage Self Synchronous Configurable Logic Blocks (SSCLB), with the introduction of a new dual tree-divider 4 input LUT to achieve a 4.5× throughput improvement over our previous model. Energy was measured at 3.23 pJ/block/cycle using a custom built board. We measured the SSFPGA for aging with accelerated degradation and results show the SSFPGA has 8% longer time margin before chip malfunctions compared to a Synchronous FPGA.