DocumentCode
2634807
Title
FPGA prototyping using behavioral synthesis for improving video processing algorithm and FHD TV SoC design
Author
Takahashi, Masaru
Author_Institution
SoC Software Platform Division, Renesas Electronics Corporation
fYear
2011
fDate
25-28 Jan. 2011
Firstpage
766
Lastpage
769
Abstract
The System on Chip (SoC) can include Full High Definition (FHD) video processing, however the turn around time of algorithm improvement have been long. We provide the new method utilizing the behavioral synthesis. Therefore, the turn around time of the algorithm improvement and hardware implementation can be shorten.
Keywords
field programmable gate arrays; high definition television; high definition video; system-on-chip; video signal processing; FHD TV SoC design; FPGA prototyping; behavioral synthesis; field programmable gate array; full high definition video processing; hardware implementation; system on chip; Algorithm design and analysis; Field programmable gate arrays; Hardware; IP networks; Streaming media; System-on-a-chip; TV;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific
Conference_Location
Yokohama
ISSN
2153-6961
Print_ISBN
978-1-4244-7515-5
Type
conf
DOI
10.1109/ASPDAC.2011.5722291
Filename
5722291
Link To Document