DocumentCode :
2634908
Title :
Rapid layout pattern classification
Author :
Jen-Yi Wuu ; Pikus, F.G. ; Torres, A. ; Marek-Sadowska, M.
Author_Institution :
Univ. of California, Santa Barbara, CA, USA
fYear :
2011
fDate :
25-28 Jan. 2011
Firstpage :
781
Lastpage :
786
Abstract :
Printability of layout objects becomes increasingly dependent on neighboring shapes within a larger and larger context window. In this paper, we propose a two-level hotspot pattern classification methodology that examines both central and peripheral patterns. Accuracy and runtime enhancement techniques are proposed, making our detection methodology robust and efficient as a fast physical verification tool that can be applied during early design stages to large-scale designs. We position our method as an approximate detection solution, similar to pattern matching-based tools widely adopted by the industry. In addition, our analyses of classification results reveal that the majority of non-hotspots falsely predicted as hotspots have printed CD barely over the minimum allowable CD threshold. Our method is verified on several 45 nm and 32 nm industrial designs.
Keywords :
circuit analysis computing; integrated circuit layout; pattern classification; pattern matching; CD threshold; fast physical verification tool; industrial designs; layout object printability; pattern matching-based tools; rapid layout pattern classification; runtime enhancement techniques; size 32 nm; size 45 nm; support vector machines; two-level hotspot pattern classification methodology; Accuracy; Layout; Pattern classification; Pixel; Runtime; Support vector machine classification; Training;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific
Conference_Location :
Yokohama
ISSN :
2153-6961
Print_ISBN :
978-1-4244-7515-5
Type :
conf
DOI :
10.1109/ASPDAC.2011.5722295
Filename :
5722295
Link To Document :
بازگشت