Session Abstract

Design technologies for integrated systems beyond the CMOS era will present new challenges to address the ever important reliability issues. For nanometer-scale processes, it is difficult to guarantee correct fabrication with an acceptable yield without employing design techniques that take into account the intrinsic existence of manufacturing defects. In order to improve the yield and reliability of systems, manufactured with nanoscale devices and wires, their interconnect infrastructures must be designed such that fabrication and life-time faults can be tolerated.