Title :
The Monsoon interconnection network
Author :
Joerg, Christopher ; Boughton, Andy
Author_Institution :
Lab. for Comput. Sci., MIT, Cambridge, MA, USA
Abstract :
The interconnection network is described for Monsoon, a parallel processing dataflow computer. This network provides reliable, high bandwidth, low latency communication between the nodes of Monsoon. The major components of this network are two gate arrays: PaRC and the data link chip (DLC). PaRC (packet switched routing chip) is a CMOS gate array that implements a 4×4 packet routing switch that provides a high raw bandwidth (800 Mb/s) to each port. PaRC is designed so that much of this bandwidth can be utilized. The DLC is a high speed ECL gate array that reliably transfers data between boards
Keywords :
CMOS integrated circuits; logic arrays; multiprocessor interconnection networks; parallel machines; 800 Mbit/s; CMOS gate array; DLC; ECL gate array; Monsoon interconnection network; PaRC; boards; data link chip; data transfer; packet routing switch; packet switched routing chip; parallel processing dataflow computer; Bandwidth; Communication switching; Computer network reliability; Computer networks; Concurrent computing; Multiprocessor interconnection networks; Packet switching; Parallel processing; Routing; Switches;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
DOI :
10.1109/ICCD.1991.139870
