A VHDL implementation of BIST technique in UART design

To increase reliability, manufacturers must be able to discover a high percentage of defective chips during their testing procedures. This paper would highlight the attention given by most customers who are expecting the designer to include testability features that will increase their product reliability. This paper focuses on the design of a UART chip with embedded built-in-self-test (BIST) architecture using FPGA technology. The paper starts by describing the behavior of UART circuit using VHISC hardware description language (VHDL). In the implementation phase, the BIST technique will be incorporated into the UART design before the overall design is synthesized by means of reconfiguring the existing design to match testability requirements.