DocumentCode
2635281
Title
Net-level reliability analysis for interconnect self-heat
Author
Jiang, Lei ; Pantuso, Daniel ; Schmitz, Anthony ; Thomas, John
Author_Institution
Design Technol. & Solutions, Intel Corp., Hillsboro, OR, USA
fYear
2012
fDate
15-19 April 2012
Abstract
A new connectivity-based design methodology is proposed to model local hotspots due to interconnect joule heating. Compared to prior CAD approach [1], it provides resistor-scale accuracy without additional design complexity impact. Results are validated with test chip data on Intel backend process.
Keywords
integrated circuit interconnections; semiconductor device reliability; Intel backend process; connectivity-based design methodology; design complexity impact; interconnect joule heating; interconnect self-heat; local hotspots; net-level reliability analysis; resistor scale accuracy; test chip data; Heating; Integrated circuit interconnections; Integrated circuit modeling; Mathematical model; Reliability; Solid modeling; Temperature measurement; circuit reliability; electromigration; joule heating; product reliability;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium (IRPS), 2012 IEEE International
Conference_Location
Anaheim, CA
ISSN
1541-7026
Print_ISBN
978-1-4577-1678-2
Electronic_ISBN
1541-7026
Type
conf
DOI
10.1109/IRPS.2012.6241890
Filename
6241890
Link To Document