DocumentCode
2635319
Title
A low-power management technique for high-performance domino circuits
Author
Tsai, Yu-Tzu ; Tsai, Cheng-Chih ; Chien, Cheng-An ; Cheng, Ching-Hwa ; Guo, Jiun-In
Author_Institution
Dept. of Electron. Eng., Feng Chia Univ., Minhsiung, Taiwan
fYear
2011
fDate
25-28 Jan. 2011
Firstpage
93
Lastpage
94
Abstract
Exploiting a charge sharing method enables a performance power management design for domino circuits. The domino circuits have both high performance and low power consumption. A test chip has been successfully validated using TSMC 0.13um CMOS technology. Reductions in dynamic power consumption of 68% and static power consumption of 15% are achieved.
Keywords
CMOS logic circuits; integrated circuit design; low-power electronics; CMOS technology; TSMC; charge sharing method; high-performance domino circuits; low-power management; test chip; CMOS integrated circuits; Clocks; Delay; Logic gates; Power demand; Semiconductor device measurement; Voltage control; domino circuit; power management;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific
Conference_Location
Yokohama
ISSN
2153-6961
Print_ISBN
978-1-4244-7515-5
Type
conf
DOI
10.1109/ASPDAC.2011.5722313
Filename
5722313
Link To Document