DocumentCode :
2635361
Title :
Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance
Author :
Liu, Chunsheng ; Huang, Yu
Author_Institution :
Comput. & Electron. Eng., Nebraska Univ.-Lincoln, Omaha, NE
fYear :
2007
fDate :
6-10 May 2007
Firstpage :
461
Lastpage :
468
Abstract :
Attack resistance has been a critical concern for security-related applications. Various side-channel attacks can he launched to retrieve security information such as encryption key. Prior work does not consider the presence of embedded compression architectures and their impacts on security. This paper analyzes the complexity of side-channel attacking on designs with embedded decompression and compaction circuit. A possible attacking strategy was first presented and performs analysis on the complexity of attacking circuits with EDT architecture. The probabilistic analysis was then extended to the more general compaction schemes using distance coding. The authors have shown that successful attacking of designs with embedded decompressor and compactor is extremely difficult. The complexity is much higher than the results shown in prior work assuming no decompression and compaction. It indicates that the use of embedded compression architectures can achieve higher security level.
Keywords :
automatic testing; cryptography; embedded systems; logic testing; attacking strategy; compaction circuit; distance coding; embedded compression architectures; embedded decompression; embedded deterministic testing; probabilistic analysis; security-related applications; side-channel attack resistance; Circuit testing; Compaction; Controllability; Cryptography; Hardware; Information retrieval; Information security; Logic testing; Observability; Protection;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2007. 25th IEEE
Conference_Location :
Berkeley, CA
ISSN :
1093-0167
Print_ISBN :
0-7695-2812-0
Type :
conf
DOI :
10.1109/VTS.2007.29
Filename :
4209954
Link To Document :
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