Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study

The need for computing power drastically increases and one solution is to use MPSoC. These MPSoCs become complex with the increase of the number of cores. Thus, designers use simulators to explore the whole platform parameters in order to define the best architecture. These simulators must be fast and accurate whatever is the architecture complexity. This paper introduces a new approximate-timed TLM approach to provide a speed up of at least x100 on the simulation time in comparison with a timed TLM approach. This new communication method allows fast and accurate hardware parameter exploration of MPSoC with a standard SystemC protocol. The lack of accuracy in networks-on-chip can affect the execution order, but the opposite slows down simulation and cannot support MPSoC exploration. For this reason, this paper focuses on networks-on-chip to demonstrate the benefits of our approximate-timed TLM approach.