• DocumentCode
    2635693
  • Title

    Combining Simulation and Virtualization through Dynamic Sampling

  • Author

    Falcón, Ayose ; Faraboschi, Paolo ; Ortega, Daniel

  • Author_Institution
    Adv. Archit. Lab., Hewlett-Packard Labs., Barcelona
  • fYear
    2007
  • fDate
    25-27 April 2007
  • Firstpage
    72
  • Lastpage
    83
  • Abstract
    The high speed and faithfulness of state-of-the-art virtual machines (VMs) make them the ideal front-end for a system simulation framework. However, VMs only emulate the functional behavior and just provide the minimal timing for the system to run correctly. In a simulation framework supporting the exploration of different configurations, a timing backend is still necessary to accurately determine the performance of the simulated target. As it has been extensively researched, sampling is an excellent approach for fast timing simulation. However, existing sampling mechanisms require capturing information for every instruction and memory access. Hence, coupling a standard sampling technique to a VM implies disabling most of the "tricks" used by a VM to accelerate execution, such as the caching and linking of dynamically compiled code. Without code caching, the performance of a VM is severely impacted. In this paper we present a novel dynamic sampling mechanism that overcomes this problem and enables the use of VMs for timing simulation. By making use of the internal information collected by the VM during functional simulation, we can quickly assess important characteristics of the simulated applications (such as phase changes), and activate or deactivate the timing simulation accordingly. This allows us to run unmodified OS and applications over emulated hardware at near-native speed, yet providing a way to insert timing measurements that yield a final accuracy similar to state-of-the-art sampling methods
  • Keywords
    sampling methods; virtual machines; code caching; dynamic sampling; fast timing simulation; virtual machines; virtualization; Acceleration; Code standards; Hardware; Joining processes; Sampling methods; Timing; Velocity measurement; Virtual machining; Virtual manufacturing; Voice mail;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Performance Analysis of Systems & Software, 2007. ISPASS 2007. IEEE International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    1-4244-1082-7
  • Electronic_ISBN
    1-4244-1082-7
  • Type

    conf

  • DOI
    10.1109/ISPASS.2007.363738
  • Filename
    4211024