Title :
New insights into gate-dielectric breakdown by electrical characterization of interfacial and oxide defects with reverse modeling methodology
Author :
Randriamihaja, Y. Mamy ; Garetto, D. ; Huard, V. ; Rideau, D. ; Roy, D. ; Rafik, M. ; Bravaix, A.
Author_Institution :
STMicroelectron., Crolles, France
Abstract :
A new methodology of defect characterization, through combination of measurements and simulations, is used to monitor the defect creation rate leading to gate-oxide breakdown. Two defect time-power creation rates were extracted, thus modifying the classical understanding of Weibull slope variation with oxide thickness. Based on our methodology, an explanation of the gate current increase prior to hard BD is proposed.
Keywords :
CMOS integrated circuits; electric breakdown; measurement systems; CMOS technology; Weibull slope variation; defect time-power creation rates; electrical characterization; gate current; gate-dielectric breakdown; hard BD; interfacial defects; measurements; oxide defects; oxide thickness; reverse modeling methodology; simulations; Analytical models; Current measurement; Electric breakdown; Logic gates; Stress; Stress measurement; Tunneling; SILC; TDDB; charge pumping; interface defects; oxide defects;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2012 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4577-1678-2
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2012.6241914