Write Pattern Format Algorithm for Reliable NAND-Based SSDs

Author

Quan Xu ; Chen, Thomas ; Yupeng Hu ; Pu Gong

Author_Institution

Sch. of Eng. & Math. Sci., City Univ. London, London, UK

Volume

61

Issue

7

fYear

2014

fDate

Jul-14

Firstpage

516

Lastpage

520

Abstract

This brief presents and evaluates a pre-coding algorithm to reduce power consumption and improve data retention in NAND-based solid-state drives. Compared to the state-of-the-art asymmetric coding and stripe pattern elimination algorithm, the proposed write pattern format algorithm (WPFA) achieves better data retention while consuming less power. The hardware for WPFA is simpler and requires less circuitry. The performance of WPFA is evaluated by both computer simulations and field-programmable gate array implementation.

Keywords

NAND circuits; circuit reliability; driver circuits; field programmable gate arrays; flash memories; precoding; NAND-based solid-state drive; WPFA; asymmetric coding; data retention; field-programmable gate array; power consumption; precoding algorithm; reliable NAND flash-based SSD; stripe pattern elimination algorithm; write pattern format algorithm; Ash; Capacitance; Complexity theory; Encoding; Field programmable gate arrays; Logic gates; Registers; NAND flash memory; power consumption; reliability; solid-state drive (SSD);

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2014.2327332

Filename

6823152