Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource Optimization

In this work, we present the implementation in a reconfigurable architecture of a dense stereo vision algorithm based on census transform. Analyzing census transform algorithm we found that size and access memory could be reduced, which consequently also reduced the latency time. Furthermore, architecture resources are optimized and efficient thanks to binary operations and integer arithmetic used by census transform directly compatible with the FPGA. Final architecture is able to construct 130 dense disparity maps per second for each corresponding pair of stereo images. A performance analysis, among other three disparity map implementations and our architecture, shows that at the end, we propose a better trade off among performance, latency, logic elements and memory size. The optimization and the resource saving rend our architecture an interesting option to solve the problem of stereo vision in real time, quite used in autonomous navigation.