• DocumentCode
    2635924
  • Title

    Reverse State Reconstruction for Sampled Microarchitectural Simulation

  • Author

    Bryan, Paul D. ; Rosier, Michael C. ; Conte, Thomas M.

  • Author_Institution
    Center for Efficient, Secure & Reliable Comput., North Carolina State Univ., Raleigh, NC
  • fYear
    2007
  • fDate
    25-27 April 2007
  • Firstpage
    190
  • Lastpage
    199
  • Abstract
    For simulation, a tradeoff exists between speed and accuracy. The more instructions simulated from the workload, the more accurate the results - but at a higher cost. To reduce processor simulation times, a variety of techniques have been introduced. Statistically sampled simulation is one method that mitigates the cost of simulation while retaining high accuracy. A contiguous group of instructions, called a cluster, is simulated and then a fast type of simulation is used to skip to the next group. As instructions are skipped, non-sampling bias is introduced and must be removed for accurate measurements to be taken. In this paper, the reverse state reconstruction warm-up method is introduced. While skipping between clusters, the data necessary for reconstruction are recorded. Later, these data are scanned in reverse order so that processor state can be approximated without functionally applying every skipped instruction. By trading storage for speed, the proposed method introduces the concept of on-demand state reconstruction for sampled simulations. Using this technique, the method isolates ineffectual instructions from the skipped instructions without the use of profiling. Compared to SMARTS, reverse state reconstruction achieves a maximum and average speedup ratio of 2.45 and 1.64, respectively, with minimal sacrifice to accuracy (less than 0.3%)
  • Keywords
    computer architecture; performance evaluation; reverse engineering; virtual machines; processor simulation; reverse state reconstruction; sampled microarchitectural simulation; Computational modeling; Computer architecture; Computer simulation; Costs; Hardware; Inspection; Microarchitecture; Process design; Research and development; Sampling methods;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Performance Analysis of Systems & Software, 2007. ISPASS 2007. IEEE International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    1-4244-1081-9
  • Electronic_ISBN
    1-4244-1082-7
  • Type

    conf

  • DOI
    10.1109/ISPASS.2007.363749
  • Filename
    4211035