Research on the problems of satellite borne FPGA based finite state machine

The FPGA design tools now wildly used would optimize finite state machinepsilas encoding style and circuit automatically to achieve better performance on timing and area, which made finite state machine full of potential dangerous for space applications. This paper propounded some design methods such as redundancy the state flip-flops and brought in third-part design tool in FPGA design flows to conquer the limitation of design tools and mitigated the SEU effect for FSM. Those methods were used and evaluated in XX_1 satellitepsilas FPGA design, which were proved effective.