Impact of well contacts on the single event response of radiation-hardened 40-nm flip-flops

Due to increased transistor packing density and small feature sizes, multiple node charge collection from an ion-strike is an important phenomenon in advanced technology nodes. It has been previously shown that well contacts efficiently drain the single-event induced charge from the system, thereby reducing the scope of single-event induced charge collection across multiple sensitive nodes. However, experimental results on a 40 nm bulk CMOS technology show that for particles with high linear-energy transfer (LET) values, absence of well contacts lowers soft-error rates in certain flip-flops at low operating frequencies. Factors affecting this mechanism are investigated through simulations and experiments.