DocumentCode :
263613
Title :
Efficient FPGA-mapping of 1024 point FFT Pipeline SDF Processor
Author :
Qureshi, Imran Ali ; Qureshi, Fahad ; Shaikh, Ghulam Muhammad
Author_Institution :
Sch. of Inf. & Electron., Beijing Inst. of Technol., Beijing, China
fYear :
2014
fDate :
13-15 July 2014
Firstpage :
29
Lastpage :
34
Abstract :
In this paper the efficient mapping of pipeline single path delay feedback (SDF) fast Fourier transform (FFT) processors to FPGAs is considered. By paying special attention to how the design can efficiently be mapped to the course grained hardware structure of a target field programmable gate array (FPGA) better implementation results can be obtained.This is illustrated by mapping a R22 SDF FFT processor, targeted towards Virtex-4 .The FPGA mapping of these designs have been explored in detail. Algorithmic transformations that provide a better mapping is proposed, resulting in implementation achievements that by far outperform earlier published work.For Virtex-4 the results show a better throughput per slice and lesser latency , still not using more memory or DSP48 resources.
Keywords :
fast Fourier transforms; field programmable gate arrays; logic design; FFT pipeline SDF processor; FPGA mapping; course grained hardware structure; fast Fourier transform; field programmable gate array; pipeline single path delay feedback; Adders; Field programmable gate arrays; Multiplexing; Pipeline processing; Pipelines; Registers; Table lookup; Single path delay feedback; Fast fourier transform; Field programmable gate array);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures, Algorithms and Programming (PAAP), 2014 Sixth International Symposium on
Conference_Location :
Beijing
ISSN :
2168-3034
Print_ISBN :
978-1-4799-3844-5
Type :
conf
DOI :
10.1109/PAAP.2014.70
Filename :
6916432
Link To Document :
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