Title :
A program for exact synthesis of three-level NAND networks
Author :
Perkowski, Marek A. ; Liu, Jiuling
Author_Institution :
Dept. of Electr. Eng., Portland State Univ., OR, USA
Abstract :
A program is described for exact minimization of three-level combinational functions from NAND (NOR) gates. This algorithm generalizes the well-known approaches of TANT synthesis in the following ways: the function is multioutput, it includes don´t cares, and any subset of variables can be available in only complemented form, or in both affirmative and complemented forms. The number of PP-implicants that can be used for exact minimum solution is reduced as a result of proving some theorems
Keywords :
NAND circuits; NOR circuits; combinatorial circuits; logic CAD; minimisation of switching nets; ternary logic; CAD; NOR gates; TANT synthesis; combinational functions; exact synthesis; minimization; multioutput function; three-level NAND networks; Algorithm design and analysis; Circuit synthesis; Design methodology; Iterative methods; Logic circuits; Logic design; Logic gates; Minimization methods; Network synthesis; Programmable logic arrays;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112313
