Variation-tolerant Design Using Residue Number System

In this paper the use of residue arithmetic is proposed as a technique to reduce delay variation in adders. It is found that the use of residue arithmetic offers significant delay variation reduction when compared to adders of the literature. Therefore this technique can be used to control variance of critical paths delay and efficiently meet timing constraints and thus improve timing yield. Experiments conducted span several values of intra-die and die-to-die variance, so that cases of practical interest for various nanoscale technologies are covered.