DocumentCode :
2636445
Title :
Reliable threshold voltage determination for sub-0.1 μm gate length MOSFETs
Author :
Tsuno, M. ; Suga, M. ; Tanaka, M. ; Shibahara, K. ; Miura-Mattausch, M. ; Hirose, M.
Author_Institution :
Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
fYear :
1998
fDate :
10-13 Feb 1998
Firstpage :
111
Lastpage :
116
Abstract :
A reliable method to determine the threshold voltage Vth for MOSFETs with gate length down to sub-0.1 μm has been developed. The method determines Vth by linear extrapolation of the transconductance gm to zero and is therefore named “GMLE method”. 2D simulations were performed to extract the physical meaning of the method and to prove its reliability for different technologies. The results reveal that determined Vth values always meet the threshold condition, i.e. the onset of inversion layer build-up
Keywords :
MOSFET; circuit CAD; circuit analysis computing; 2D simulations; MOSFETs; inversion layer build-up; linear extrapolation; reliability; threshold condition; threshold voltage; transconductance; Current measurement; Data mining; Extrapolation; Linearity; Low voltage; MOSFET circuits; Subthreshold current; Threshold voltage; Transconductance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-4425-1
Type :
conf
DOI :
10.1109/ASPDAC.1998.669419
Filename :
669419
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2636445
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